As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements such as flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers, as shown in U.S. Pat. No. 4,503,537. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test (CUT) works properly.
For ICs containing only digital components, testing can be a fairly straightforward process using the techniques described above. Testing of analog circuitry, on the other hand, poses special challenges. Analog testing carries greater uncertainty and variability of results when compared with digital testing because of the fundamental differences between analog and digital components. While detecting a faulty digital circuit can be as simple as detecting the difference between 0 and 1, analog components, or nodes, in functioning circuits have a continuous range of acceptable values, with an infinite number of values possible within the limits of the range.
Furthermore, modem integrated circuits have become so densely packed with logic that traditional testing methods no longer suffice. Using external automated testing equipment (ATE) to input test data and to read back and analyze test output is becoming prohibitively expensive in terms of time, pin overhead (additional pins needed for input and output of test data) and overall cost. Furthermore, the traditional “bed of nails” approach to testing analog circuits is no longer workable because the layout of modern integrated circuits restricts direct physical access to the analog nodes from outside the chip.
Previously developed methods of analog or mixed signal testing have been unsatisfactory for today's system on a chip (SoC) applications. In some methods, the analog or mixed signal circuitry is divided into functional blocks, with each block containing additional or modified circuitry to turn the block into an oscillator, which then indicates whether the block is functioning correctly. However, such methods have the drawback of requiring modification of each block under test, therefore incurring high additional overhead in terms of design time and chip area. Other methods have been proposed in which checker circuits are added to each individual analog node to test the functionality of the node. But again, high overhead cost makes such methods undesirable, especially in systems with large number of analog components. Moreover, the testing methods described above are unable to accurately detect a full range of fault types. While some methods are able to detect permanent faults and some parametric faults, other parametric faults and most intermittent faults can not be successfully exposed.
Thus, while integrated circuit designs incorporate ever-increasing numbers of analog nodes, the development of efficient testing methodology continues to lag behind. Minimizing chip area and design-time overhead while maximizing the accuracy and completeness of testing are of critical importance.